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Third Party CINI - "EUPEX - EUROPEAN PILOT FOR EXASCALE" (H2020-JTI-EuroHPC-2020-1)

Progetto
The EUPEX consortium aims to design, build, and validate the first EU platform for HPC, covering end-to-end the spectrum of required technologies with European assets: from the architecture, processor, system software, development tools to the applications. The EUPEX prototype will be designed to be open, scalable and flexible, including the modular OpenSequanacompliant platform and the corresponding HPC software ecosystem for the Modular Supercomputing Architecture. Scientifically, EUPEX is a vehicle to prepare HPC, AI, and Big Data processing communities for upcoming European Exascale systems and technologies. The hardware platform is sized to be large enough for relevant application preparation and scalability forecast, and a proof of concept for a modular architecture relying on European technologies in general and on European Processor Technology (EPI) in particular. In this context, a strong emphasis is put on the system software stack and the applications. Being the first of its kind, EUPEX sets the ambitious challenge of gathering, distilling and integrating European technologies that the scientific and industrial partners use to build a production-grade prototype. EUPEX will lay the foundations for Europe's future digital sovereignty. It has the potential for the creation of a sustainable European scientific and industrial HPC ecosystem and should stimulate science and technology more than any national strategy (for numerical simulation, machine learning and AI, Big Data processing). The EUPEX consortium – constituted of key actors on the European HPC scene – has the capacity and the will to provide a fundamental contribution to the consolidation of European supercomputing ecosystem. EUPEX aims to directly support an emerging and vibrant European entrepreneurial ecosystem in AI and Big Data processing that will leverage HPC as a main enabling technology.
  • Dati Generali
  • Aree Di Ricerca
  • Pubblicazioni

Dati Generali

Partecipanti (7)

ALDINUCCI Marco   Responsabile scientifico  
BIRKE Robert Renè Maria   Partecipante  
BONO Viviana   Partecipante  
BOSIO Lorenzo   Partecipante  
DONATELLI Susanna   Partecipante  
HORVATH Andras   Partecipante  
RABELLINO Sergio   Partecipante  

Referenti (2)

LO IACONO Cristiano   Amministrativo  
ROCHAS Fabio   Amministrativo  

Dipartimenti coinvolti

INFORMATICA   Principale  

Tipo

H2020 Research and Innovation action

Finanziatore

EUROPEAN COMMISSION
Ente Finanziatore

Partner

Università degli Studi di TORINO

Contributo Totale (assegnato) Ateneo (EURO)

150.625€

Periodo di attività

Gennaio 1, 2022 - Dicembre 31, 2025

Durata progetto

48 mesi

Aree Di Ricerca

Settori (10)


72.19.09 - Ricerca e sviluppo sperimentale nel campo delle altre scienze naturali e dell'ingegneria

PE6_2 - Computer systems, parallel/distributed systems, sensor networks, embedded systems, cyber-physical systems - (2020)

PE6_3 - Software engineering, operating systems, computer languages - (2020)

PE6_6 - Algorithms, distributed, parallel and network algorithms, algorithmic game theory - (2020)

Settore INF/01 - Informatica

CIBO, AGRICOLTURA e ALLEVAMENTI - Farmacologia Veterinaria

ECONOMIA, AZIENDE E ORGANIZZAZIONI - Sistemi e metodologie per la Qualità

INFORMATICA, AUTOMAZIONE e INTELLIGENZA ARTIFICIALE - Digitalizzazione della Società e della Pubblica Amministrazione

INFORMATICA, AUTOMAZIONE e INTELLIGENZA ARTIFICIALE - Industria X.0

INFORMATICA, AUTOMAZIONE e INTELLIGENZA ARTIFICIALE - Salute e Informatica

Parole chiave (3)

parallel and distributed computing
parallel and distributed systems
software and systems engineering
No Results Found

Pubblicazioni

Pubblicazioni (4)

Toward HPC application portability via C++ PSTL: the Gaia AVU-GSR code assessment 
THE JOURNAL OF SUPERCOMPUTING
2024
Articolo
Partially Open Access
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The MPI + CUDA Gaia AVU-GSR Parallel Solver Toward Next-generation Exascale Infrastructures 
PUBLICATIONS OF THE ASTRONOMICAL SOCIETY OF THE PACIFIC
2023
Articolo
Open Access
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Performance portability via C++ PSTL, SYCL, OpenMP, and HIP: the Gaia AVU-GSR case study 
IEEE - INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS
2024
Contributo in Atti di convegno
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Towards formal model for location aware workflows 
HOSSAIN SHAHRIAR, YUUICHI TERANISHI, ALFREDO CUZZOCREA, MOUSHUMI SHARMIN, DAVE TOWEY, AKM JAHANGIR ALAM MAJUMDER, HIROKI KASHIWAZAKI, JI-JIANG YANG, MICHIHARU TAKEMOTO, NAZMUS SAKIB, RYOHEI BANNO, SHEIKH IQBAL AHAMED
2023
Contributo in Atti di convegno
Open Access
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